Partial List of Published Papers


2024

  1. “An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated Circuits”, In Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’24). (Zhenyu Xu, Miaoxiang Yu, Jillian Cai, Saddam Gafsi, Judson Douglas Ryckman, Qing Yang, and Tao Wei).
  2. Machine Learning in Sensors for Collision Avoidance”, (Erkan Karakus, Tao Wei and Qing Yang), in Proceedings of International Conference on Computing, Networking and Communications (ICNC 2024) pp. 291-295

2023

  • “A Novel FPGA Simulator Accelerating Reinforcement Learning-Based Design of Power Converters”. Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays. (Zhenyu Xu, Miaoxiang Yu, Qing Yang, Yeonho Jeong, Tao Wei)

2022

  • “A Novel FPGA-Based Circuit Simulator for Accelerating Reinforcement Learning-Based Design of Power Converters”. 34th IEEE International Conference on Application-specific Systems, Architectures and Processors.. Porto, Portugal. (Zhenyu Xu, Miaoxiang Yu, Qing Yang, Yeonho Jeong, Jillian Cai and Tao Wei)
  • “A Novel Interconnection Architecture for Secured Die-to-Die Communication in System-in-Package. 2022 IEEE International Conference on Networking, Architecture and Storage (NAS). (Zhenyu Xu, Qing Yang, Tao Wei)
  • “Highly Scalable Runtime Countermeasure Against Microprobing Attacks on Die-to-Die Interconnections in System-in-Package”, Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. (Zhenyu Xu, Thomas Mauldin, Qing Yang, Tao Wei)
  • “A Novel Interconnection Architecture for Secured Die-to-Die Communication in System-in-Package”
  • Zhenyu Xu, Tao Wei and Qing Yang, 16th IEEE International Conference on Networking, Architecture and Storage, Oct 3-4, 2022, Philadelphia, USA.
  • “In-Sensor Neural Network Preprocessing for ADAS Computer Systems” , Mark Bruckner, Erkan Karakus, Tao Wei and Qing Yang, 16th IEEE International Conference on Networking, Architecture and Storage, 2022, Philadelphia, USA.

2020 

2019 

2018

2017 

2015 

2014 

2013 

2012 

2011

2010 

2009

2008 

2007 

2006 

2005 

2004 

2003 

2002 

2001 

2000 

1999 

1998

1997 

1996 

  • Y. Hu and Qing Yang, “DCD—Disk Caching Disk: A New Approach for Boosting I/O Performance,” The 23rd Annual International Symposium on Computer Architecture, Philadelphia PA May, 1996. (ISCA’96)S.
  • Ray, H. Jiang and Q. Yang, “A Compiler-directed Approach to Network La tency Reduction in Distributed Shared Memory Multiprocessors”, Journal of Parallel and Distributed Computing, Special Issue on Compilation Techniques for Distributed Memory Systems. 38-2:267-276, 1996 
  • Li Yang, X. Pei, and Qing Yang, “Performance Analysis of A new Disk Architecture as A Netserver for NFS Network Systems” Int’l Conference on Computer Applications in Industry and Engineering (CAINE-96), Dec. 1996.
  • C-M Chung, D-A Chiang and Qing Yang “A comparative analysis of different arbitration protocols for multiple-bus multiprocessors” International Journal of Computer Science and Enigeering. Vol. 11, No. 3,May 1996.

1995

1994 

  • Chenyi Hu, Baker Kearfott, Joe Sheldon and Qing Yang, “Solving nonlinear systems on vector supercomputers,” Proc. Int’l Conf. on Parallel and Distributed Computing, Oct. 1994.
  • Sibabrata Ray, Hong Jiang and Qing Yang, “A New Approach To Network Latency Reduction of Multiprocessors by Data Migration in The Absence of Cache Coherence Mechanisms” Proc. Int’l Conf. on Parallel and Distributed Computing, Oct. 1994.
  • T. Sun and Q. Yang, “Evaluating cache performance for vector computers,” Proc. Int’l Conf. on Parallel and Distributed Computing, Oct. 1994.
  • N. Annupindi, M. An, J. W. Cooley and Qing Yang, “A new and efficient FFT algorithm for distributed memory systems,” Proceedings of Internation Conference on Parallel and Distributed Systems, Dec. 1994, Taiwan
  • T. Sun and Q. Yang, “A comparison of cached and uncached vector computers,” Proceedings of IEEE 1994 Int’l Conf. on Parallel and Distributed Systems, Oct. 1994.
  • Q. Yang and S. Adina, “A one’s complement cache,” Proceedings of 94′ Int’l Conf. on Parallel Processing, Aug. 1994.
  • Q. Gan, Q. Yang and C. Y. Hu, “Parallel all-row preconditioned interval linear solver for nonlinear equations on multiprocessors,” Parallel Computing, (20) 1994.
  • Xiaoshu Qian and Qing Yang, “An analytical model for load balancing on sy mmetric multiprocessor systems,” Journal of Parallel and Distributed Computing, Vol. 20, 1994, pp. 198-211.

1993 

  • Qing Yang, “Introducing a new cache design into vector computers,” IEEE Transactions on Computers, Vol. 42, No. 12, Dec. 1993, pp. 1411-1424. The Prime-mapped Cache 
  • Qing Yang, “Guest Editor’s Introduction,” IEEE Computer Society Tech. Comm. on Comp. Arch. Newsletter, Special Issue on Cache Memories for Supercomputers, Oct. 1993.
  • Qing Yang, “Performance of cache memories for vector computers,” Journal of Parallel and Distributed Computing, Special Issue on Performance of Supercomputers. 19 pp.163-178, 1993.
  • Qing Yang and H. Wang, “A graph approach to minimizing processor fragmen tations on hypercube multiprocessors”, IEEE Transactions on Parallel and Distributed Systems, Oct. 1993, pp. 1165-1171.

1992

  •  Q. Yang and Liping W. Yang, “A novel cache design for vector processing,” The 19th International Symposium on Computer Architecture, May 1992, pp. 362-371. Gold Coast, Austrilia. (ISCA’92)
  • H. Wang and Q. Yang, “On fault tolerant computation of orthogonal transforms on hypercube multiprocessors,” Proc. of 21th Int’l Conf. on Parallel Processing, Vol. 1, Aug. 1992.
  • Qing Yang, D. Ghosal, and S. K. Tripathi, “Performance study of two protocols for voice/data integration on ring networks “, Computer Networks and ISDN Vol. 23, 1992, pp. 267-285.
  • Qing Yang, G. Thangadurai and L. N. Bhuyan, “Design of a dynamic cache co herence scheme for large scale multiprocessors”, IEEE Transactions on Parallel and Distributed Systems, Vol. 3, No. 3, May 1992, pp.281-293.

1991 

  • Q. Yang, “Effects of arbitration protocols on the performance of multiple-bus multiprocessors,” Proc. of 20th Int’l Conf. on Parallel Processing, Vol. 1, 1991.
  • H. Wang and Q. Yang, “A Prime-Cube graph approach for processor allocation in hypercube multiprocessors,” Proc. of 20th Int’l Conf. on Parallel Processing, Vol. 1, pp. 25-32, 1991.
  • Qing Yang and X. Qian, “Load balancing on distributed multiprocessor architectures with LAL”, Proc. on 11th Int,l Conf. on Distributed Computing Systems, May 1991, pp. 402-409.
  • C. Hu, M. Bayoumi, B. Kearfott and Q. Yang, “A parallelized algorithm for the preconditioned interval Newton method,” Proc. 5th SIAM Conf. on Parallel Processing, March, 1991.
  • Qing Yang and L. N. Bhuyan, “Analysis of Packet-Switched Multiple-Bus Mult iprocessor Systems,” IEEE Transactions on Computers, Vol. 30, No. 3, March 1991, pp. 352-357.

1990 

  • Q. Yang, G. Thangadurai and L. N. Bhuyan, “An adaptive cache coherence scheme for hierarchical shared-memory multiprocessors,” IEEE Symp. on Parallel Processing, Dec. 1990.
  • Qing Yang and R. Ravi, “Design and analysis of multiple-bus arbiters with different priority schemes”, Proc. of PARBASE-90–Int. Conf. on Database, Parallel Architectures, and Their Applications, pp 238-247 March, 1990.
  • Q. Yang, “On performance improvement of cache coherence protocols for hierarchical multiprocessors,” ISMM Int’l Conf. on Parallel and Distributed Computing, and Systems, Oct. 1990.
  • Qing Yang, “Performance analysis of a cache coherent multiprocessor based on hierarchical buses”, Proc. of PARBASE-90–Int. Conf. on Database, Parallel Architectures, and Their Applications, pp 248-257 March, 1990.
  • Qing Yang and L. N. Bhuyan, “Performance of Multiple-Bus Interconnections for Multiprocessors,” Journal of Parallel and Distributed Computing, 8. pp. 267-273 (1990).

1989 

  • Qing Yang, L. N. Bhuyan and B. Liu, “Analysis and Comparison of Cache Cohe rence Protocols for a Packet-Switched Multiprocessor,” IEEE Transactions on Computers, Special Issue on Distributed Computer Systems, A ug. 1989, pp 1143-1153
  • .L. N. Bhuyan, D. Ghosal, and Qing Yang, “Approximate Analysis of Single a nd Multiple-ring Networks,” IEEE Transactions on Computers, July 1989, pp 1027-1040.
  • L. N. Bhuyan, Qing Yang and D. P. Agrawal, “Performance of Multiprocessor Interconnection Networks”, IEEE Computer, Feb. 1989.

1988 

  • Q. Yang and L.N. Bhuyan, “A queueing network model for cache coherence protocol on asynchronous multiple-bus multiprocessors,” 88’Int,l Conf. on Parallel Processing, pp. 130-137, 1988.
  • Qing Yang and S. G. Zaky, “Communication performance in multiple-bus systems”, IEEE Transactions on Computers, Vol. 32, No. 7, pp. 848-853, July 1988.

1987 

  • Q. Yang, L.N. Bhuyan, and R. Pavaskar, “Performance analysis of packet switched multiple-bus multiprocessor systems,” Proceedings of Eighth Real-Time System Symposium, Dec. 1987, pp. 170-178.
  • Q. Yang and L.N. Bhuyan, “Design and analysis of decentralized multiple-bus multiprocessor,” Proceedings of 87’Int’l Conf. on Parallel Processing, Aug. 1987, pp. 889-892.

1986 

  • Q. Yang, D. Ghosal and L.N. Bhuyan, “Analysis of Multiple Token-ring and Multiple Slotted-ring Networks,” IEEE Proceedings Computer Networking Symposium, Washington D.C., Nov. 1986, pp 79-86.